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ltc6409 1 6409fa ltc6409 driving ltc2262-14 adc, f in = 70mhz, C1dbfs, f s = 150mhz, 4096-point fft typical a pplica t ion descrip t ion 10ghz gbw, 1.1nv/ hz differential amplifier/adc driver the ltc ? 6409 is a very high speed, low distortion, dif - ferential amplifier. its input common mode range includes ground, so that a ground-referenced input signal can be dc-coupled, level-shifted, and converted to drive an adc differentially. the gain and feedback resistors are external, so that the exact gain and frequency response can be tailored to each application. for example, the amplifier could be externally compensated in a no-overshoot configuration, which is desired in certain time-domain applications. the ltc6409 is stable in a differential gain of 1. this al - lows for a low output noise in applications where gain is not desired. it draws 52ma of supply current and has a hardware shutdown feature which reduces current con - sumption to 100a. the ltc6409 is available in a compact 3mm 2mm 10 - pin leadless qfn package and operates over a C40c to 125c temperature range. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. dc-coupled interface from a ground-referenced single-ended input to an ltc2262-14 adc fea t ures a pplica t ions n 10ghz gain-bandwidth product n 88db sfdr at 100mhz, 2v p-p n 1.1nv/hz input noise density n input range includes ground n external resistors set gain (min 1v/v) n 3300v/s differential slew rate n 52ma supply current n 2.7v to 5.25v supply voltage range n fully differential input and output n adjustable output common mode voltage n low power shutdown n small 10-lead 3mm 2mm 0.75mm qfn package n differential pipeline adc driver n high-speed data-acquisition cards n automated test equipment n time domain reflexometry n communications receivers + ? ? + 150 1.3pf ltc6409 v ocm = 0.9v v in 33.2 33.2 10 10 150 150 150 6409 ta01 a in + a in ? ltc2262-14 adc gnd v dd 1.8v 3.3v 1.3pf 39pf 39pf frequency (mhz) 6409 ta01b amplitude (dbfs) 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?90 ?100 ?110 ?120 0 70 40 10 50 20 60 30 v s = 3.3v v outdiff = 1.8v p-p hd2 = ?86.5dbc hd3 = ?89.4dbc sfdr = 81.6db snr = 71.1db
ltc6409 2 6409fa symbol parameter conditions min typ max units v osdiff differential offset voltage (input referred) v s = 3v v s = 3v v s = 5v v s = 5v l l 300 300 1000 1200 1100 1400 v v v v v osdiff t differential offset voltage drift (input referred) v s = 3v v s = 5v l l 2 2 v/c v/c i b input bias current (note 6) v s = 3v v s = 5v l l C140 C160 C62 C70 0 0 a a i os input offset current (note 6) v s = 3v v s = 5v l l 2 2 10 10 a a r in input resistance common mode differential mode 165 860 k c in input capacitance differential mode 0.5 pf e n differential input noise voltage density f = 1mhz, not including r i /r f noise 1.1 nv/ hz i n input noise current density f = 1mhz, not including r i /r f noise 8.8 pa/hz nf noise figure at 100mhz shunt-terminated to 50, r s = 50, r i = 25, r f = 10k 6.9 db p in c on f igura t ion a bsolu t e maxi m u m r a t ings total supply voltage (v + C v C ) ................................. 5. 5v input current (+in, Cin, v ocm , shdn ) (note 2) ................................................................ 1 0ma output short-circuit duration (note 3) ............ in definite operating temperature range (note 4) .................................................. C 40c to 125c specified temperature range (note 5) .................................................. C 40c to 125c maximum junction temperature .......................... 15 0c storage temperature range .................. C 65c to 150c top view udb package 10-lead (3mm 2mm) plastic qfn ?out +in +out ?in v ? v + v ? shdn v + v ocm 7 11,v ? 6 10 9 8 1 2 3 4 5 t jmax = 150c, ja = 138c/w, jc = 5.2c/w exposed pad (pin 11) connected to v C o r d er i n f or m a t ion e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, v C = 0v, v cm = v ocm = v icm = 1.25v, v shdn = open. v s is defined as (v + C v C ). v outcm is defined as (v +out + v Cout )/2. v icm is defined as (v +in + v Cin )/2. v outdiff is defined as (v +out C v Cout ). (note 1) lead free finish tape and reel (mini) tape and reel part marking* package description specified temperature range ltc6409cudb#trmpbf ltc6409cudb#trpbf lfpf 10-lead (3mm 2mm) plastic qfn 0c to 70c ltc6409iudb#trmpbf ltc6409iudb#trpbf lfpf 10-lead (3mm 2mm) plastic qfn C40c to 85c ltc6409hudb#trmpbf ltc6409hudb#trpbf lfpf 10-lead (3mm 2mm) plastic qfn C40c to 125c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc6409 3 6409fa e lec t rical c harac t eris t ics symbol parameter conditions min typ max units e nvocm common mode noise voltage density f = 10mhz 12 nv/ hz v icmr (note 7) input signal common mode range v s = 3v v s = 5v l l 0 0 1.5 3.5 v v cmrri (note 8) input common mode rejection ratio (input referred) v icm /v osdiff v s = 3v, v icm from 0v to 1.5v v s = 5v, v icm from 0v to 3.5v l l 75 75 90 90 db db cmrrio (note 8) output common mode rejection ratio (input referred) v ocm /v osdiff v s = 3v, v ocm from 0.5v to 1.5v v s = 5v, v ocm from 0.5v to 3.5v l l 55 60 80 85 db db psrr (note 9) differential power supply rejection (v s /v osdiff ) v s = 2.7v to 5.25v l 60 85 db psrrcm (note 9) output common mode power supply rejection (v s /v oscm ) v s = 2.7v to 5.25v l 55 70 db v s supply voltage range (note 10) l 2.7 5.25 v g cm common mode gain (v outcm /v ocm ) v s = 3v, v ocm from 0.5v to 1.5v v s = 5v, v ocm from 0.5v to 3.5v l l 1 1 v/v v/v g cm common mode gain error, 100 (g cm C 1) v s = 3v, v ocm from 0.5v to 1.5v v s = 5v, v ocm from 0.5v to 3.5v l l 0.1 0.1 0.3 0.3 % % bal output balance (v outcm / v outdiff ) v outdiff = 2v single-ended input differential input l l C65 C70 C50 C50 db db v oscm common mode offset voltage (v outcm C v ocm ) v s = 3v v s = 5v l l 1 1 5 6 mv mv v oscm t common mode offset v oltage drift l 4 v/c v outcmr (note 7) output signal common mode range (voltage range for the v ocm pin) v s = 3v v s = 5v l l 0.5 0.5 1.5 3.5 v v r invocm input resistance, v ocm pin l 30 40 50 k v ocm self-biased voltage at the v ocm pin v s = 3v, v ocm = open v s = 5v, v ocm = open l 0.9 0.85 1.25 1.6 v v v out output voltage, high, either output pin v s = 3v, i l = 0 v s = 3v, i l = C20ma v s = 5v, i l = 0 v s = 5v, i l = C20ma l l l l 1.85 1.8 3.85 3.8 2 1.95 4 3.95 v v v v output voltage, low, either output pin v s = 3v, 5v; i l = 0 v s = 3v, 5v; i l = 20ma l l 0.06 0.2 0.15 0.4 v v i sc output short-circuit current, either output pin (note 11) v s = 3v v s = 5v l l 50 70 70 95 ma ma a vol large-signal open loop voltage gain 65 db i s supply current l 52 56 58 ma ma i shdn supply current in shutdown v shdn 0.6v l 100 500 a r shdn shdn pull-up resistor v shdn = 0v to 0.5v l 115 150 185 k v il shdn input logic low l 0.6 v v ih shdn input logic high l 1.4 v t on turn-on time 160 ns t off turn-off time 80 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, v C = 0v, v cm = v ocm = v icm = 1.25v, v shdn = open. v s is defined as (v + C v C ). v outcm is defined as (v +out + v Cout )/2. v icm is defined as (v +in + v Cin )/2. v outdiff is defined as (v +out C v Cout ).
ltc6409 4 6409fa e lec t rical c harac t eris t ics symbol parameter conditions min typ max units sr slew rate differential output, v outdiff = 4v p-p +out rising (Cout falling) +out falling (Cout rising) 3300 1720 1580 v/s v/s v/s gbw gain-bandwidth product r i = 25, r f = 10k, f test = 100mhz l 9.5 8 10 ghz ghz f C3db C3db frequency r i = r f = 150, r load = 400, c f = 1.3pf 2 ghz f 0.1db frequency for 0.1db flatness r i = r f = 150, r load = 400 , c f = 1.3pf 600 mhz fpbw full power bandwidth v outdiff = 2v p-p 550 mhz hd2 hd3 25mhz distortion differential input, v outdiff = 2v p-p , r i = r f = 150, r load = 400 2nd harmonic 3rd harmonic C104 C106 dbc dbc 100mhz distortion differential input, v outdiff = 2v p-p , r i = r f = 150, r load = 400 2nd harmonic 3rd harmonic C93 C88 dbc dbc hd2 hd3 25mhz distortion single-ended input, v outdiff = 2v p-p , r i = r f = 150, r load = 400 2nd harmonic 3rd harmonic C101 C103 dbc dbc 100mhz distortion single-ended input, v outdiff = 2v p-p , r i = r f = 150, r load = 400 2nd harmonic 3rd harmonic C88 C93 dbc dbc imd3 3rd order imd at 25mhz f1 = 24.9mhz, f2 = 25.1mhz v outdiff = 2v p-p envelope, r i = r f = 150, r load = 400 C110 dbc 3rd order imd at 100mhz f1 = 99.9mhz, f2 = 100.1mhz v outdiff = 2v p-p envelope, r i = r f = 150, r load = 400 C98 dbc 3rd order imd at 140mhz f1 = 139.9mhz, f2 = 140.1mhz v outdiff = 2v p-p envelope, r i = r f = 150, r load = 400 C88 dbc oip3 equivalent oip3 at 25mhz (note 12) equivalent oip3 at 100mhz (note 12) equivalent oip3 at 140mhz (note 12) 59 53 48 dbm dbm dbm t s settling time v outdiff = 2v p-p step, r i = r f = 150, r load = 400 1% settling 1.9 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, v C = 0v, v cm = v ocm = v icm = 1.25v, v shdn = open. v s is defined as (v + C v C ). v outcm is defined as (v +out + v Cout )/2. v icm is defined as (v +in + v Cin )/2. v outdiff is defined as (v +out C v Cout ). note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: input pins (+in, Cin, v ocm , and shdn) are protected by steering diodes to either supply. if the inputs should exceed either supply voltage, the input current should be limited to less than 10ma. in addition, the inputs +in, Cin are protected by a pair of back-to-back diodes. if the differential input voltage exceeds 1.4v, the input current should be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. note 4: the ltc6409c/ltc6409i are guaranteed functional over the temperature range of C40c to 85c. the ltc6409h is guaranteed functional over the temperature range of C40c to 125c. note 5: the ltc6409c is guaranteed to meet specified performance from 0c to 70c. the ltc6409c is designed, characterized and expected to meet specified performance from C40c to 85c, but is not tested or qa sampled at these temperatures. the ltc6409i is guaranteed to meet specified performance from C40c to 85c. the ltc6409h is guaranteed to meet specified performance from C40c to 125c. note 6: input bias current is defined as the average of the input currents flowing into the inputs (Cin and +in). input offset current is defined as the difference between the input currents (i os = i b + C i b C ).
ltc6409 5 6409fa typical p er f or m ance c harac t eris t ics supply current vs supply voltage supply current vs shdn voltage shutdown supply current vs supply voltage differential input offset voltage vs temperature differential input offset voltage vs input common mode voltage common mode offset voltage vs temperature e lec t rical c harac t eris t ics note 7: input common mode range is tested by testing at both v icm = 1.25v and at the electrical characteristics table limits to verify that the differential offset (v osdiff ) and the common mode offset (v oscm ) have not deviated by more than 1mv and 2mv respectively from the v icm = 1.25v case. the voltage range for the output common mode range is tested by applying a voltage on the v ocm pin and testing at both v ocm = 1.25v and at the electrical characteristics table limits to verify that the common mode offset (v oscm ) has not deviated by more than 6mv from the v ocm = 1.25v case. note 8: input cmrr is defined as the ratio of the change in the input common mode voltage at the pins +in or Cin to the change in differential input referred offset voltage. output cmrr is defined as the ratio of the change in the voltage at the v ocm pin to the change in differential input referred offset voltage. this specification is strongly dependent on feedback ratio matching between the two outputs and their respective inputs and it is difficult to measure actual amplifier performance (see effects of resistor pair mismatch in the applications information section of this data sheet). for a better indicator of actual amplifier performance independent of feedback component matching, refer to the psrr specification. note 9: differential power supply rejection (psrr) is defined as the ratio of the change in supply voltage to the change in differential input referred offset voltage. common mode power supply rejection (psrrcm) is defined as the ratio of the change in supply voltage to the change in the output common mode offset voltage. note 10: supply voltage range is guaranteed by power supply rejection ratio test. note 11: extended operation with the output shorted may cause the junction temperature to exceed the 150c limit. note 12: refer to relationship between different linearity metrics in the applications information section of this data sheet for information on how to calculate an equivalent oip3 from imd3 measurements. temperature (c) 6409 g01 differential v os (mv) v s = 5v v ocm = v icm = 1.25v r i = r f = 150 five representative units ?50 50 125100 ?25 0 25 75 1.5 1.0 0.5 0 ?0.5 input common mode voltage (v) 6409 g02 differential v os (mv) v s = 5v v ocm = 1.25v r i = r f = 150 0.1% feedback network resistors representative unit 0 2 4 3 0.5 1 1.5 2.5 3.5 2.0 1.5 1.0 0.5 ?0.5 0 ?1.0 t a = 85c t a = 70c t a = 25c t a = 0c t a = ?40c supply voltage (v) 6409 g04 total supply current (ma) v shdn = open 0 2 5.5 3.53 0.5 1 1.5 2.5 4 54.5 60 20 15 25 30 35 40 45 50 55 10 5 0 t a = 125c t a = 85c t a = 70c t a = 25c t a = 0c t a = ?40c shdn voltage (v) 6409 g05 v s = 5v total supply current (ma) 0 2 5 3.53 0.5 1 1.5 2.5 4 4.5 60 20 15 25 30 35 40 45 50 55 10 5 0 t a = 125c t a = 85c t a = 70c t a = 25c t a = 0c t a = ?40c supply voltage (v) 6409 g06 shutdown supply current (a) v shdn = v ? 0 2 5.5 3.53 0.5 1 1.5 2.5 4 54.5 140 120 100 80 60 20 40 0 t a = 125c t a = 85c t a = 70c t a = 25c t a = 0c t a = ?40c temperature (c) 6409 g03 common mode offset voltage (mv) v s = 5v v ocm = v icm = 1.25v r i = r f = 150 five representative units 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?50 50 125100 ?25 0 25 75
ltc6409 6 6409fa typical p er f or m ance c harac t eris t ics large signal step response overdriven output transient response cmrr vs frequency differential psrr vs frequency small signal step response differential output voltage noise vs frequency differential output impedance vs frequency frequency (hz) voltage noise density (nv/ hz) 1k 1g 1m 1 6409 g07 v s = 5v r i = r f = 150 includes r i /r f noise 1000 100 10 1 20ns/div 6409 g14 voltage (v) 4.0 0.5 3.5 2.5 1.5 3.0 2.0 1.0 0 +out ?out v s = 5v v ocm = 1.25v r load = 200 to ground per output frequency (mhz) 6409 g09 output impedance () v s = 5v r i = r f = 150 1000 100 10 1 0.01 0.1 1 100 10 1000 10000 1 100 10 1000 10000 frequency (mhz) 6409 g10 cmrr (db) v s = 5v v ocm = 1.25v r i = r f = 150, c f = 1.3pf 0.1% feedback network resistors 100 90 80 70 60 50 1 100 10 1000 10000 frequency (mhz) 6409 g11 psrr (db) v s = 5v 90 80 70 60 50 10 30 20 40 2ns/div 6409 g12 20mv/div +out ?out v s = 5v v ocm = v icm = 1.25v r load = 400 r i = r f = 150, c f = 1.3pf c l = 0pf v in = 200mv p-p , differential 0.2v/div 2ns/div 6409 g13 +out ?out v s = 5v r load = 400 v in = 2v p-p , differential input noise density vs frequency frequency (hz) input voltage noise density (nv/ hz) input current noise density (pa/ hz) 1k 1g 1m 1 6409 g18 i n e n v s = 5v 1000 100 10 1 1000 100 10 1
ltc6409 7 6409fa frequency response vs closed loop gain frequency response vs load capacitance gain 0.1db flatness typical p er f or m ance c harac t eris t ics harmonic distortion vs frequency harmonic distortion vs output common mode voltage harmonic distortion vs input amplitude frequency (mhz) 6409 g19 distortion (dbc) v s = 5v v ocm = v icm = 1.25v r load = 400 r i = r f = 150 v outdiff = 2v p-p differential inputs ?50 ?60 ?70 ?80 ?90 ?120 ?110 ?100 1 1000 100 10 hd2 hd3 output common mode voltage (v) 6409 g20 distortion (dbc) ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?110 ?100 0.5 3.532.521.51 v s = 5v f in = 100mhz r load = 400 r i = r f = 150 v outdiff = 2v p-p differential inputs hd2 hd3 input amplitude (dbm) 6409 g21 distortion (dbc) ?80 ?90 ?120 ?110 ?100 ?4 (0.4v p-p ) ?2 10 (2v p-p ) 86420 v s = 5v v ocm = v icm = 1.25v f in = 100mhz r load = 400 r i = r f = 150 differential inputs hd2 hd3 1 100 10 1000 10000 frequency (mhz) 6409 g15 gain (db) v s = 5v v ocm = v icm = 1.25v r load = 400 60 50 40 30 20 10 0 ?30 ?20 ?10 a v = 1 a v = 2 a v = 5 a v = 10 a v = 20 a v = 100 a v = 400 a v (v/v) c f (pf) r i () r f () 1 2 5 10 20 100 400 150 100 50 50 25 25 25 150 200 250 500 500 2.5k 10k 1.3 1 0.8 0.4 0.4 0 0 10 1000 100 10000 frequency (mhz) 6409 g16 gain (db) 20 10 0 ?30 ?20 ?10 v s = 5v v ocm = v icm = 1.25v r load = 400 r i = r f = 150, c f = 1.3pf capacitor values are from each output to ground. no series resistors are used. c l = 0pf c l = 0.5pf c l = 1pf c l = 1.5pf c l = 2pf 1 100 10 1000 10000 frequency (mhz) 6409 g17 gain (db) 0.5 0.1 0.2 0.3 0.4 0 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 v s = 5v v ocm = v icm = 1.25v r load = 400 r i = r f = 150, c f = 1.3pf slew rate vs temperature ?50 50 125100 ?25 0 25 75 temperature (c) 6409 g08 slew rate (v/s) v s = 5v 3400 3200 3225 3250 3275 3300 3325 3350 3375
ltc6409 8 6409fa p in func t ions +in, Cin (pins 2, 6): non-inverting and inverting input pins. shdn (pin 3): when shdn is floating or directly tied to v + , the ltc6409 is in the normal (active) operating mode. when the shdn pin is connected to v C , the part is disabled and draws approximately 100a of supply current. v + , v C (pins 4, 9 and pins 8, 10): positive and negative power supply pins. similar pins should be connected to the same voltage. v ocm (pin 5): output common mode reference voltage. the voltage on this pin sets the output common mode voltage level. if left floating, an internal resistor divider develops a default voltage of 1.25v with a 5v supply. +out, Cout (pins 7, 1): differential output pins. exposed pad (pin 11): tie the bottom pad to v C . if split supplies are used, do not tie the pad to ground. intermodulation distortion vs frequency intermodulation distortion vs output common mode voltage intermodulation distortion vs input amplitude typical p er f or m ance c harac t eris t ics ?50 ?60 ?70 ?80 ?90 ?120 ?110 ?100 frequency (mhz) 6409 g25 third order imd (dbc) v s = 5v v ocm = v icm = 1.25v r load = 400 r i = r f = 150 2 tones, 200khz tone spacing, 2v p-p composite differential inputs 10 1000 100 v s = 5v v ocm = v icm = 1.25v r load = 400 r i = r f = 150 v outdiff = 2v p-p single-ended input 0.5 3.532.521.51 output common mode voltage (v) 6409 g26 third order imd (dbc) v s = 5v f in = 100mhz r load = 400 r i = r f = 150 2 tones, 200khz tone spacing, 2v p-p composite differential inputs ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?110 ?100 input amplitude (dbm) ?80 ?90 ?120 ?110 ?100 2 (0.8v p-p ) 10 (2v p-p ) 8 6 4 6409 g27 third order imd (dbc) v s = 5v v ocm = v icm = 1.25v f in = 100mhz r load = 400 r i = r f = 150 2 tones, 200khz tone spacing differential inputs harmonic distortion vs frequency harmonic distortion vs output common mode voltage harmonic distortion vs input amplitude frequency (mhz) 6409 g22 distortion (dbc) v s = 5v v ocm = v icm = 1.25v r load = 400 r i = r f = 150 v outdiff = 2v p-p single-ended input ?50 ?60 ?70 ?80 ?90 ?120 ?110 ?100 1 1000 100 10 hd2 hd3 output common mode voltage (v) 6409 g23 distortion (dbc) ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?110 ?100 0.5 3.532.521.51 v s = 5v f in = 100mhz r load = 400 r i = r f = 150 v outdiff = 2v p-p single-ended input hd2 hd3 input amplitude (dbm) 6409 g24 distortion (dbc) ?80 ?90 ?120 ?110 ?100 ?4 (0.4v p-p ) ?2 10 (2v p-p ) 86420 v s = 5v v ocm = v icm = 1.25v f in = 100mhz r load = 400 r i = r f = 150 single-ended input hd2 hd3
ltc6409 9 6409fa b lock diagra m a pplica t ions i n f or m a t ion functional description the ltc6409 is a small outline, wideband, high speed, low noise, and low distortion fully-differential amplifier with accurate output phase balancing. the amplifier is optimized to drive low voltage, single-supply, differential input analog- to-digital converters (adcs). the ltc6409 input common mode range includes ground, which makes it ideal to dc-couple and convert ground-referenced, single-ended signals into differential signals that are referenced to the user-supplied output common mode voltage. this is ideal for driving these differential adcs. the balanced differential nature of the amplifier also provides even-order harmonic distortion cancellation, and low susceptibility to common mode noise (like power supply noise). the ltc6409 can operate with a single-ended input and differential output, or with a differential input and differential output. the outputs of the ltc6409 are capable of swinging from close-to-ground to 1v below v + . they can source or sink up to approximately 70ma of current. load capacitances should be decoupled with at least 10 of series resistance from each output. input pin protection the ltc6409 input stage is protected against differential input voltages which exceed 1.4v by two pairs of series diodes connected back to back between +in and Cin. moreover, the input pins, as well as v ocm and shdn pins, have clamping diodes to either power supply. if these pins are driven to voltages which exceed either supply, the current should be limited to 10ma to prevent damage to the ic. shdn pin the shdn pin is a cmos logic input with a 150k internal pull-up resistor. if the pin is driven low, the ltc6409 pow - ers down. if the pin is left unconnected or driven high, the part is in normal active operation. some care should be taken to control leakage currents at this pin to prevent inadvertently putting the ltc6409 into shutdown. the turn-on and turn-off time between the shutdown and ac- tive states is typically less than 200ns. general amplifier applications in figure 1, the gain to v outdiff from v inp and v inm is given by: v outdiff = v +out ? v ?out r f r i ? v inp ? v inm ( ) (1) note from equation (1), the differential output voltage (v +out C v Cout ) is completely independent of input and output common mode voltages, or the voltage at the common mode pin. this makes the ltc6409 ideally v + v ? v + v ? ? + 6 ?in 5 v ocm 4 v + v + 3 shdn 10 v ? v ? 9 v + v + 8 v ? v ? 7 +out 2 +in 1 ?out 200k 50k 6409 bd
ltc6409 10 6409fa a pplica t ions i n f or m a t ion that can be processed is even wider. the input common mode range at the op amp inputs depends on the circuit configuration (gain), v ocm and v cm (refer to figure 1). for fully differential input applications, where v inp = Cv inm , the common mode input is approximately: v icm = v +in + v ?in 2 v ocm ? r i r i + r f + v cm ? r f r i + r f with single-ended inputs, there is an input signal com- ponent to the input common mode voltage. applying only v inp (setting v inm to zero), the input common mode voltage is approximately: v icm = v +in + v ?in 2 v ocm ? r i r i + r f + v cm ? r f r i + r f + v inp 2 ? r f r i + r f (2) this means that if, for example, the input signal (v inp ) is a sine, an attenuated version of that sine signal also appears at the op amp inputs. input impedance and loading effects the low frequency input impedance looking into the v inp or v inm input of figure 1 depends on how the inputs are driven. for fully differential input sources (v inp = Cv inm ), the input impedance seen at either input is simply: r inp = r inm = r i for single-ended inputs, because of the signal imbalance at the input, the input impedance actually increases over the balanced differential case. the input impedance looking into either input is: r inp = r inm = r i 1? 1 2 ? r f r i + r f input signal sources with non-zero output impedances can also cause feedback imbalance between the pair of feedback networks. for the best performance, it is recommended that the input source output impedance be compensated. if input impedance matching is required by the source, figure 1. circuit for common mode range ? + r f v ?out v +out v vocm v ocm 6409 f01 r f r i r i + ? v inp + ? v cm ? + v inm v ?in v +in suited for pre-amplification, level shifting and conversion of single-ended signals to differential output signals for driving differential input adcs. output common mode and v ocm pin the output common mode voltage is defined as the aver - age of the two outputs: v outcm = v ocm = v +out + v ?out 2 as the equation shows, the output common mode voltage is independent of the input common mode voltage, and is instead determined by the voltage on the v ocm pin, by means of an internal common mode feedback loop. if the v ocm pin is left open, an internal resistor divider develops a default voltage of 1.25v with a 5v supply. the v ocm pin can be overdriven to another voltage if desired. for example, when driving an adc, if the adc makes a reference available for setting the common mode voltage, it can be directly tied to the v ocm pin, as long as the adc is capable of driving the 40k input resistance presented by the v ocm pin. the electrical characteristics table specifies the valid range that can be applied to the v ocm pin (v outcmr ). input common mode voltage range the ltc6409s input common mode voltage (v icm ) is defined as the average of the two input pins, v +in and v Cin . the valid range that can be used for v icm has been specified in the electrical characteristics table (v icmr ). however, due to external resistive divider action of the gain and feedback resistors, the effective range of signals
ltc6409 11 6409fa a pplica t ions i n f or m a t ion a termination resistor r t should be chosen (see figure 2) such that: r t = r inm ? r s r inm ? r s according to figure 2, the input impedance looking into the differential amp (r inm ) reflects the single-ended source case, given above. also, r2 is chosen as: r2 = r t ||r s = r t ? r s r t + r s figure 2. optimal compensation for signal source impedance b is defined as the difference in the feedback factors: ? = r i2 r i2 + r f2 ? r i1 r i1 + r f1 here, v cm and v indiff are defined as the average and the difference of the two input voltages v inp and v inm , respectively: v cm = v inp + v inm 2 v indiff = v inp C v inm when the feedback ratios mismatch (b), common mode to differential conversion occurs. setting the differential input to zero (v indiff = 0), the degree of common mode to differential conversion is given by the equation: v outdiff = v +out ? v ?out (v cm ? v ocm ) ? ? avg (3) in general, the degree of feedback pair mismatch is a source of common mode to differential conversion of both signals and noise. using 0.1% resistors or better will mitigate most problems and will provide about 54db worst case of common mode rejection. a low impedance ground plane should be used as a reference for both the input signal source and the v ocm pin. there may be concern on how feedback factor mismatch affects distortion. feedback factor mismatch from using 1% resistors or better, has a negligible effect on distortion. however, in single supply level shifting applications where there is a voltage difference between the input common mode voltage and the output common mode voltage, v s + ? ? + r f r f r i r inm r s r i r2 = r s || r t r t chosen so that r t || r inm = r s r2 chosen to balance r t || r s r t 6409 f02 effects of resistor pair mismatch figure 3 shows a circuit diagram which takes into consid - eration that real world resistors will not match perfectly. assuming infinite open loop gain, the differential output relationship is given by the equation: v outdiff = v +out ? v ?out v indiff ? r f r i + v cm ? ? avg ? v ocm ? ? avg where r f is the average of r f1 , and r f2 , and r i is the average of r i1 , and r i2 . b avg is defined as the average feedback factor from the outputs to their respective inputs: avg = 1 2 ? r i1 r i1 + r f1 + r i2 r i2 + r f2 ? ? ? ? ? ? figure 3. real-world application with feedback resistor pair mismatch ? + r f2 v ?out v +out v vocm v ocm 6409 f03 r f1 r i2 r i1 + ? v inp ? + v inm v ?in v +in
ltc6409 12 6409fa resistor mismatch can make the apparent voltage offset of the amplifier appear worse than specified. the apparent input referred offset induced by feedback factor mismatch is derived from equation (3): v osdiff(apparent) (v cm C v ocm ) ? b using the ltc6409 in a single 5v supply application with 0.1% resistors, the input common mode grounded, and the v ocm pin biased at 1.25v, the worst case mismatch can induce 1.25mv of apparent offset voltage. noise and noise figure the ltc6409s differential input referred voltage and current noise densities are 1.1nv/ hz and 8.8pa/ hz , respectively. in addition to the noise generated by the amplifier, the surrounding feedback resistors also contribute noise. a simplified noise model is shown in figure 4. the output noise generated by both the amplifier and the feedback components is given by the equation: e no = e ni s 1+ r f r i ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 + 2 s i n s r f ( ) 2 + 2 s e nri s r f r i ? ? ? ? ? ? 2 + 2 s e nrf 2 if the circuits surrounding the amplifier are well balanced, common mode noise (e nvocm ) of the amplifier does not appear in the differential output noise equation given above. a plot of this equation and a plot of the noise generated by the feedback components for the ltc6409 are shown in figure 5. the ltc6409s input referred voltage noise contributes the equivalent noise of a 75 resistor. when the feedback network is comprised of resistors whose values are larger than this, the output noise is resistor noise and amplifier current noise dominant. for feedback networks consist- ing of resistors with values smaller than 75, the output noise is voltage noise dominant (see figure 5). lower resistor values always result in lower noise at the penalty of increased distortion due to increased loading by the feedback network on the output. higher resistor values will result in higher output noise, but typically im- proved distortion due to less loading on the output. for this reason, when ltc6409 is configured in a differential gain of 1, using feedback resistors of at least 150 is recommended. to calculate noise figure (nf), a source resistance and the noise it generates should also come into consideration. figure 6 shows a noise model for the amplifier which includes the source resistance (r s ). to generalize the a pplica t ions i n f or m a t ion figure 4. simplified noise model ? + e no 2 r f v ocm e nri 2 r f r i r i e nrf 2 e nri 2 e ni 2 e nrf 2 i n+ 2 i n? 2 6409 f04 figure 5. ltc6409 output noise vs noise contributed by feedback network alone r i = r f () noise density (nv/ hz) 6409 f05 1000 100 10 1 0.1 10 1000 10000 100 total (amplifier and feedback network) output noise feedback network noise
ltc6409 13 6409fa finally, noise figure can be obtained as: nf = 10log 1 + e no 2 e no 2 (rs) ? ? ? ? ? ? ? ? figure 7 specifies the measured total output noise (e no ), excluding the noise contribution of source resistance, and noise figure (nf) of ltc6409 configured at closed loop gains (a v = r f /r i ) of 1v/v, 2v/v and 5v/v. the circuits in the left column use termination resistors and transform- ers to match to the 50 source resistance, while the circuits in the right column do not have such matching. for simplicity, dc-blocking and bypass capacitors have not been shown in the circuits, as they do not affect the noise results. relationship between different linearity metrics linearity is, of course, an important consideration in many amplifier applications. this section relates the inter- modulation distortion of fully differential amplifiers to other linearity metrics commonly used in rf style blocks. intercept points are specifications that have long been used as key design criteria in the rf communications world as a metric for the intermodulation distortion performance of a device in the signal chain (e.g., amplifiers, mixers, etc.). intercept points, like noise figures, can be easily cascaded back and forth through a signal chain to determine the overall performance of a receiver chain, thus resulting in simpler system-level calculations. traditionally, these systems use primarily single-ended rf amplifiers as gain blocks designed to operate in a 50? environment, just like the rest of the receiver chain. since intercept points are given in dbm, this implies an associated impedance of 50?. however, for ltc6409 as a differential feedback amplifier with low output impedance, a 50? resistive load is not re- quired (unlike an rf amplifier). this distinction is important when evaluating the intercept point for ltc6409. in fact, the ltc6409 yields optimum distortion performance when loaded with 200? to 1k? (at each output), very similar to the input impedance of an adc. as a result, terminating a pplica t ions i n f or m a t ion figure 6. a more general noise model including source and termination resistors calculation, a termination resistor (r t ) is included and its noise contribution is taken into account. now, the total output noise power (excluding the noise contribution of r s ) is calculated as: e no 2 = e ni ? 1+ r f r i + r t ||r s 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 + 2 ? i n ? r f ( ) 2 + 2 ? e nri ? r f r i + r t ||r s 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 + 2 ? e nrf 2 + e nrt ? r f r i ? 2r i ||r s r t + 2r i ||r s ( ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 meanwhile, the output noise power due to noise of r s is given by: e no 2 (rs) = e nrs ? r f r i ? 2r i ||r t r s + 2r i ||r t ( ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 ? + e no 2 r f v ocm e nri 2 r f r i r i r s e nrf 2 e nrs 2 r t e nrt 2 e nri 2 e ni 2 e nrf 2 i n + 2 i n ? 2 6409 f06
ltc6409 14 6409fa a pplica t ions i n f or m a t ion the input of the adc to 50? can actually be detrimental to system performance. the definition of 3rd order intermodulation distortion (imd3) is shown in figure 8. also, a graphical repre- sentation of how to relate imd3 to output/input 3rd order intercept points (oip3/iip3) has been depicted in figure 9. based on this figure, equation (4) gives the definition of the intercept point, relative to the intermodu - lation distortion. oip3 = p o + imd3 2 (4) p o is the output power of each of the two tones at which imd3 is measured, as shown in figure 9. it is calculated in dbm as: p o = 10log v 2 pdiff 2 ? r l ? 10 ?3 ? ? ? ? ? ? (5) where r l is the differential load resistance, and v pdiff is the differential peak voltage for a single tone. normally, intermodulation distortion is specified for a benchmark composite differential peak of 2v p-p at the output of the 50 v in + ? 50 v in + ? ? + 150 1.3pf 150 150 150 50 1:4 6409 f07 1.3pf v ocm v in + ? 600 e no = 4.70nv/ hz nf = 14.41db ? + 200 1pf 200 100 100 50 1:4 1pf v ocm v in + ? e no = 5.77nv/ hz nf = 10.43db ? + 500 500 100 100 50 1:4 v ocm v in + ? e no = 11.69nv/ hz nf = 8.81db ? + 150 1.3pf 150 150 150 50 1.3pf v ocm v in + ? e no = 5.88nv/ hz nf = 17.59db ? + 200 1pf 200 100 100 1pf 0.4pf 0.4pf 0.8pf 0.8pf v ocm e no = 9.76nv/ hz nf = 16.66db ? + 250 250 50 50 v ocm e no = 14.23nv/ hz nf = 13.56db figure 7. ltc6409 measured output noise and noise figure at different closed loop gains with and without source impedance matching
ltc6409 15 6409fa r s 50 v s r f ltc6409 100 100 r f c f r i r i r t r l 50 c ba 6409 f10 1db loss ideal 4:1 ideal 1:4 1db loss + ? c f r t a pplica t ions i n f or m a t ion figure 8. definition of imd3 figure 9. graphical representation of the relationship between imd3 and oip3 amplifier, implying that each single tone is 1v p-p , result- ing in v pdiff = 0.5v. using r l = 50? as the associated impedance, p o is calculated to be close to 4dbm. as seen in equation (5), when a higher impedance is used, the same level of intermodulation distortion performance results in a lower intercept point. therefore, it is impor - tant to consider the impedance seen by the output of the ltc6409 when working with intercept points. comparing linearity specifications between different am- plifier types becomes easier when a common impedance level is assumed. for this reason, the intercept points for ltc6409 are reported normalized to a 50? load im - pedance. this is the reason why oip3 in the electrical characteristics table is 4dbm more than half the absolute value of imd3. if the top half of the ltc6409 demo board (dc1591a, shown in figure 12) is used to measure imd3 and oip3, one should make sure to properly convert the power seen at the differential output of the amplifier to the power that appears at the single-ended output of the demo board. figure 10 shows an equivalent representation of the top half of the demo board. this view ignores the dc-blocking and bypass capacitors, which do not affect the analysis here. the transmission line transformers (used mainly for impedance matching) are modeled here as ideal 4:1 impedance transformers together with a C1db block. this separates the insertion loss of the transformer from its ideal behavior. the 100 resistors at the ltc6409 output create a differential 200 resistance, which is an imped- ance match for the reflected r l . as previously mentioned, imd3 is measured for 2v p-p dif- ferential peak (i.e. 10dbm) at the output of the ltc6409, corresponding to 1v p-p (i.e. 4dbm) at each output alone. from ltc6409 output (location a in figure 10) to the input of the output transformer (location b), there is a voltage attenuation of 1/2 (or C6db) formed by the resistive divider figure 10. equivalent schematic of the top half of the ltc6409 demo board p s power frequency imd3 = p s ? p o ?f = f2 ? f1 = f1 ? (2f1 ? f2) = (2f2 ? f1) ? f2 6409 f08 p s p o p o 2f1 ? f2 2f2 ? f1 f1 f2 imd3 1 iip3 p o oip3 p out (dbm) p in (dbm) 6409 f10 p s 3
ltc6409 16 6409fa a pplica t ions i n f or m a t ion between the r l ? 4 = 200 differential resistance seen at location b and the 200 formed by the two 100 match- ing resistors at the ltc6409 output. thus, the differential power at location b is 10 C 6 = 4dbm. since the transformer ratio is 4:1 and it has an insertion loss of about 1db, the power at location c (across r l ) is calculated to be 4 C 6 C 1 = C3dbm. this means that imd3 should be measured while the power at the output of the demo board is C3dbm which is equivalent to having 2v p-p differential peak (or 10dbm) at the output of the ltc6409. gbw vs f C3db gain-bandwidth product (gbw) and C3db frequency (f C3db ) have been both specified in the electrical characteristics table as two different metrics for the speed of the ltc6409. gbw is obtained by measuring the gain of the amplifier at a specific frequency (f test ) and calculate gain ? f test . to measure gain, the feedback factor (i.e. b = r i /(r i + r f )) is chosen sufficiently small so that the feedback loop does not limit the available gain of the ltc6409 at f test , ensuring that the measured gain is the open loop gain of the amplifier. as long as this condition is met, gbw is a parameter that depends only on the internal design and compensation of the amplifier and is a suitable metric to specify the inherent speed capability of the amplifier. f C3db , on the other hand, is a parameter of more practi- cal interest in different applications and is by definition the frequency at which the gain is 3db lower than its low frequency value. the value of f C3db depends on the speed of the amplifier as well as the feedback factor. since the ltc6409 is designed to be stable in a differential signal gain of 1 (where r i = r f or b = 1/2), the maximum f C3db is obtained and measured in this gain setting, as reported in the electrical characteristics table. in most amplifiers, the open loop gain response exhibits a conventional single-pole roll-off for most of the frequen- cies before crossover frequency and the gbw and f C3db numbers are close to each other. however, the ltc6409 is intentionally compensated in such a way that its gbw is significantly larger than its f C3db . this means that at lower frequencies (where the input signal frequencies typically lie, e.g. 100mhz) the amplifiers gain and the thus the feedback loop gain is larger. this has the important advantage of further linearizing the amplifier and improving distortion at those frequencies. looking at the frequency response vs closed loop gain graph in the typical performance characteristics section of this data sheet, one sees that for a closed loop gain (a v ) of 1 (where r i = r f = 150?), f C3db is about 2ghz. however, for a v = 400 (where r i = 25? and r f = 10k?), the gain at 100mhz is close to 40db = 100v/v, implying a gbw value of 10ghz. feedback capacitors when the ltc6409 is configured in low differential gains, it is often advantageous to utilize a feedback capacitor (c f ) in parallel with each feedback resistor (r f ). the use of c f implements a pole-zero pair (in which the zero frequency is usually smaller than the pole frequency) and adds posi - tive phase to the feedback loop gain around the amplifier. therefore, if properly chosen, the addition of c f boosts the phase margin and improves the stability response of the feedback loop. for example, with r i = r f = 150?, it is recommended for most general applications to use c f = 1.3pf across each r f . this value has been selected to maximize f C3db for the ltc6409 while keeping the peaking of the closed loop gain versus frequency response under a reasonable level (<1db). it also results in the highest frequency for 0.1db gain flatness (f 0.1db ). however, other values of c f can also be utilized and tailored to other specific applications. in general, a larger value for c f reduces the peaking (overshoot) of the amplifier in both frequency and time domains, but also decreases the closed loop bandwidth (f C3db ). for example, while for a closed loop gain (a v ) of 5, c f = 0.8pf results in maximum f C3db (as previously shown in the frequency response vs closed loop gain graph of this data sheet), if c f = 1.2pf is used, the amplifier exhibits no overshoot in the time domain which is desirable in certain applications. both the circuits discussed in this section have been shown in the typical applications section of this data sheet.
ltc6409 17 6409fa a pplica t ions i n f or m a t ion board layout and bypass capacitors for single supply applications, it is recommended that high quality 0.1f||1000pf ceramic bypass capacitors be placed directly between each v + pin and its closest v C pin with short connections. the v C pins (including the exposed pad) should be tied directly to a low impedance ground plane with minimal routing. for dual (split) power supplies, it is recommended that additional high quality 0.1f||1000pf ceramic capacitors be used to bypass v + pins to ground and v C pins to ground, again with minimal routing. for driving heavy differential loads (<200), additional bypass capacitance may be needed for optimal perfor - mance. keep in mind that small geometry (e.g., 0603) surface mount ceramic capacitors have a much higher self-resonant frequency than do leaded capacitors, and perform best in high speed applications. to prevent degradation in stability response, it is highly recommended that any stray capacitance at the input pins, +in and Cin, be kept to an absolute minimum by keeping printed circuit connections as short as possible. this becomes especially true when the feedback resistor network uses resistor values greater than 500 in circuits with r i = r f . at the output, always keep in mind the differential nature of the ltc6409, because it is critical that the load impedances seen by both outputs (stray or intended), be as balanced and symmetric as possible. this will help preserve the balanced operation of the ltc6409 that minimizes the generation of even-order harmonics and maximizes the rejection of common mode signals and noise. the v ocm pin should be bypassed to the ground plane with a high quality ceramic capacitor of at least 0.01f. this will prevent common mode signals and noise on this pin from being inadvertently converted to differential signals and noise by impedance mismatches both externally and internally to the ic. driving adcs the ltc6409s ground-referenced input, differential output and adjustable output common mode voltage make it ideal for interfacing to differential input adcs. these adcs are typically supplied from a single-supply voltage and have an optimal common mode input range near mid-supply. the ltc6409 interfaces to these adcs by providing single- ended to differential conversion and common mode level shifting. the sampling process of adcs creates a transient that is caused by the switching in of the adc sampling capaci- tor. this momentarily shorts the output of the amplifier as charge is transferred between amplifier and sampling capacitor. the amplifier must recover and settle from this load transient before the acquisition period has ended, for a valid representation of the input signal. the ltc6409 will settle quickly from these periodic load impulses. the rc network between the outputs of the driver and the inputs of the adc decouples the sampling transient of the adc (see figure 11). the capacitance serves to provide the bulk of the charge during the sampling process, while the two resistors at the outputs of the ltc6409 are used to dampen and attenuate any charge injected by the adc. the rc filter gives the additional benefit of band limiting broadband output noise. generally, longer time constants improve snr at the expense of settling time. the resistors in the decoupling network should be at least 10. these resistors also serve to decouple the ltc6409 outputs from load capacitance. too large of a resistor will leave insufficient settling time. too small of a resistor will not properly dampen the load transient of the sampling process, prolonging the time required for settling. in 16 - bit applica- tions, this will typically require a minimum of eleven rc time constants. for lowest distortion, choose capacitors with low dielectric absorption (such as a c0g multilayer ceramic capacitor).
ltc6409 18 6409fa ? + 3 shdn 6 ?in 7 +out 2 +in 1 ?out a in + a in ? 150 4 v + v + v + 5v v ocm v ocm 10 v ? 8 v ? v ? v ? 6409 f11 ltc6409 adc ltc2262-14 v in shdn 150 150 100 150 0.1f 33.2 33.2 10 10 5v 5 0.1f||1000pf 0.1f||1000pf control gnd v dd v cm d13 ? ? d0 0.1f||1000pf 39pf 39pf 1.8v 1f 1.3pf 1.3pf 1f 9 v + a pplica t ions i n f or m a t ion figure 11. driving an adc
ltc6409 19 6409fa j5 +in j6 ?in r38 opt r37 0 r32 opt r31 0 r39 150, 0.1% r33 150, 0.1% r6 opt j8 +out r7 0 jp1 en dis e2 v cm e4 v ocm e3 gnd e1 v + ?in +in +out ?out r5 150, 0.1% c22 1.3pf v ocm ltc6409udb 6 2 5 3 8 10 4 9 11 1 7 r3 100 r4 100 r11 300 r9 150, 0.1% r10 150, 0.1% 6409 f12 c18 0.1f c19 0.1f c23 0.1f c24 0.1f c26 0.1f c27 1.3pf c28 0.1f r15 opt r16 opt r13 opt r12 300 c32 0.1f r8 150, 0.1% r17 10 shdn shdn1 v ? v + v ? v + v + v + t1 tcm4-19 1:4 xfmr mini-circuits v ? j1 in 1 2 3 c25 0.1f sd 3 ct 2 s pd p 1 r14 0 r2 opt t2 tcm4-19 4:1 xfmr mini-circuits j2 out c29 0.1f s1 ct2 sd p pd 4 6 6 4 3 r1 0 jp2 en dis ?in +in +out ?out r28 150, 0.1% c13 1.3pf v ocm v ocm ltc6409udb 6 2 5 3 8 10 4 9 11 1 7 c2 0.01f c4 0.47f c6 0.01f c8 0.47f c1 100pf c3 0.1f c5 100pf c7 0.1f c11 0.1f c12 10f c9 1000pf c10 1000pf c17 1.3pf c16 0.1f r29 150, 0.1% r30 10 shdn shdn2 v ? v + v ? v + v + v + v ? 1 2 3 r35 opt j7 ?out r36 0 r40 50 r34 50 r23 300 r21 75 r24 75 c14 0.1f c15 0.1f c31 0.1f c20 0.1f r19 opt r20 300 r25 300 r22 300 t3 tcm4-19 1:4 xfmr mini-circuits j3 cal in c30 0.1f sd 3 ct 2 s pd p 1 r18 0 r26 opt t4 tcm4-19 4:1 xfmr mini-circuits j4 cal out calibration path c21 0.1f s1 ct2 sd p pd 4 6 6 4 3 r27 0 figure 12. demo board dc1591a schematic a pplica t ions i n f or m a t ion
ltc6409 20 6409fa a pplica t ions i n f or m a t ion figure 13. demo board dc1591a layout
ltc6409 21 6409fa typical a pplica t ions dc-coupled level shifting of an i/q demodulator output 6409 ta02 c2 10pf c1 10pf rf in 1900mhz ?10dbm 200mv p-p c3 12pf r5 620 r6 620 c5 0.9pf c4 0.9pf diff output z 130 | | 2.5pf dc level 1.25v dc level 3.9v dc level 3.4v gain: 12.3db gain: 1.1db r3 75 r4 75 r1 75 r2 75 ?out +out identical q channel 5v 5pf 65 5pf 65 ? + + ? 5v ltc6409 v ocm 1.25v 5v i 5v 5pf 65 5pf 65 5v q 5v lt5575 lo 1920mhz 0dbm ?8.9dbm 227mv p-p 3.4dbm 936mv p-p single-ended to differential conversion using ltc6409 and 50mhz lowpass filter (only one channel shown) ltm9011-14 f3 f1 f2 c1 c2 b3 b1 b2 v cm12 a in2 + a in2 ? a in3 + a in3 ? v cm34 a in4 + a in4 ? a in8 + a in8 ? a in1 + a in1 ? o1a + o1a ? dco + dco ? fr + fr ? g2 g1 n1 n2 h7 h8 g8 g7 e7 e8 clk + clk ? p5 p6 b6 c5 1.8v 1.8v sense v dd v ref ov dd 33pf 150pf 180nh 180nh 3.3v 180nh 180nh 150pf 150 474 37.4 37.4 ?out +out v ocm +in v + ?in 474 75 75 66.5 66.5 0.1f 0.8pf 0.8pf 68pf 68pf 6409 ta03 ?? ? ?? ? + 150 shdn gnd input 49.9 ltc6409
ltc6409 22 6409fa p ackage descrip t ion 0.40 0.10 0.50 0.10 0.80 bsc bottom view?exposed pad side view 0.75 0.05 r = 0.13 typ 0.20 ref (udb10) dfn 0910 rev a 0.70 0.10 1 2 35 6 7 8 10 0.60 0.10 3.00 0.05 0.90 0.10 detail a 0.25 0.10 0.05 0.10 2.00 0.05 detail a 0.25 0.05 0.50 bsc 0.00 ? 0.05 0.90 0.05 detail b 0.25 0.05 0.05 0.05 0.25 0.05 0.85 0.05 recommended solder pad pitch and dimensions 3.50 0.05 1.10 0.05 0.65 0.05 0.75 0.05 2.50 0.05 package outline 0.50 bsc detail b 0.95 0.05 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package udb package 10-lead plastic qfn (3mm 2mm) (reference ltc dwg # 05-08-1848 rev a)
ltc6409 23 6409fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 12/10 revised typical application drawing 21
ltc6409 24 6409fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 1210 rev a ? printed in usa r ela t e d p ar t s typical a pplica t ions ltc6409 externally compensated for maximum gain flatness and for no-overshoot time-domain response part number description comments ltc6400-8/ltc6400-14/ ltc6400-20/ltc6400-26 1.8ghz low noise, low distortion, differential adc drivers C71dbc im3 at 240mhz 2v p-p composite, i s = 90ma, a v = 8db/14db/20db/26db ltc6401-8/ltc6401-14/ ltc6401-20/ltc6401-26 1.3ghz low noise, low distortion, differential adc drivers C74dbc im3 at 140mhz 2v p-p composite, i s = 50ma, a v = 8db/14db/20db/26db ltc6406/ltc6405 3ghz/2.7ghz low noise, rail-to-rail input differential amplifier/driver C70dbc/C65dbc distortion at 50mhz, i s = 18ma, 1.6nv/ hz noise, 3v/5v supply LTC6416 2ghz low noise, differential 16-bit adc buffer C72.5dbc im3 at 300mhz 2v p-p composite, 150mw on 3.6v supply ltc2209 16-bit, 160msps adc 100db sfdr, v dd = 3.3v, v cm = 1.25v ltc2262-14 14-bit, 150msps ultralow power 1.8v adc 88db sfdr, 149mw, v dd = 1.8v, v cm = 0.9v 1 100 10 1000 10000 frequency (mhz) gain (db) 0.5 0.1 0.2 0.3 0.4 0 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 + ? ? + 250 1.2pf ltc6409 v ocm = 1.25v 150 150 channel 1 50 channel 2 50 49.9 v in 50 50 250 6409 ta04 tektronix csa8200 scope 5v 0.1f 0.1f 0.1f 0.1f 0.4v p-p 1.2pf 50 + ? ? + 150 1.3pf ltc6409 v ocm = 1.25v 150 150 port 3 50 port 4 50 75 150 150 150 1/2 agilent e5071a port 1 50 port 2 50 1/2 agilent e5071a 5v 0.1f 0.1f 0.1f 0.1f 1.3pf 75 0.2v/div 2ns/div + ? +out ?out gain 0.1db flatness no-overshoot step response

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